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General
08 Sep 2026
One Chip, One Datacenter: Meta and Panmnesia Extend Tight Coupling Beyond the Rack with CXL — Published by Invitation from Nature
Panmnesia, a fabless semiconductor company, and Meta, a global hyperscaler, have jointly proposed a next-generation artificial intelligence datacenter architecture in which an entire datacenter operates like a single chip. The work appears as an invited Review in Nature Reviews Electrical Engineering (NREE), a Nature Portfolio journal.
Research
03 Jul 2026
Panmnesia Unveils Silicon-Proven Results Validating CXL’s Practicality; Meta Also Shares Real-World Deployment Results at ISCA
As AI agents, large language models (LLMs), and similar technologies see widespread use in everyday life, demand for memory capacity is climbing to unprecedented levels. In fact, according to Meta's own analysis, roughly 40% of data-center servers are unable to deliver their full performance because they run short of memory capacity.
Research
24 Jun 2026
“Bringing More CXL Memory within the Same Latency Class” Panmnesia Unveils Next-Stage CXL Switch and Controller at ISCA 2026
Panmnesia (CEO Myoungsoo Jung) will present its next-stage CXL* controller and a fabric switch** built on it at ISCA 2026. ISCA (the International Symposium on Computer Architecture), a leading conference in the field, runs from June 27 to July 1 this year in Raleigh, USA.
Event
28 Apr 2026
Panmnesia Unveils Link Solutions for Agentic AI at ISPASS 2026 Keynote
Panmnesia (CEO Myoungsoo Jung), an AI infrastructure link solutions company, unveiled its link solutions for agentic AI during its ISPASS 2026 keynote on the 28th, titled "From Generative to Agentic AI - The Memory-Centric Turn in Datacenter Design." The core of the proposal is to reduce data access overhead by storing and managing large-scale KV caches within a memory pool built on Panmnesia's CXL switches and controllers.
General
16 Apr 2026
Panmnesia Supplies Pre-Release Silicon of PCIe 6.4-CXL 3.2 Fusion Switch ... World’s Only ASIC Switch Chip with Port-Based Routing(PBR) and Full CXL 3.2 Standard Compliance
Panmnesia (CEO Myoungsoo Jung), a South Korean fabless company developing link solutions for AI infrastructure, announced that it supplies pre-release silicon of its PCIe 6.4-CXL 3.2 fusion switch. The chip is the world's only silicon to fully implement the CXL 3.2 specification, including Port-Based Routing (PBR).
General
09 Apr 2026
Panmnesia Expands Into AI Accelerator Interconnects Including UALink and Ethernet, Securing ~$10M R&D Project for Controller and Switch SoC Development
Panmnesia, a company specializing in AI semiconductor interconnect technologies, announced that it has secured an approximately $10M R&D project focused on next-generation interconnect technologies for AI data centers. R&D project focused on next-generation interconnect technologies for AI data centers. The project encompasses the development of Link Controllers and Switches based on open standards such as UALink (Ultra Accelerator Link) and Ethernet-based interconnect protocols.
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