Panmnesia Unveils Silicon-Proven Results Validating CXL’s Practicality; Meta Also Shares Real-World Deployment Results at ISCA
Share
As AI agents, large language models (LLMs), and similar technologies see widespread use in everyday life, demand for memory capacity is climbing to unprecedented levels. In fact, according to Meta's own analysis, roughly 40% of data-center servers are unable to deliver their full performance because they run short of memory capacity.
Against this backdrop, memory-centric interconnects that can lower the cost of memory expansion are drawing intense interest from both industry and academia. Among them, the most prominent approach is expanding memory over CXL*.
In this environment, Panmnesia, a fabless startup, validated the performance of its own silicon-based CXL controller and switch. Separately, Meta, a global hyperscaler, unveiled the results of a real-world deployment of CXL silicon chips in its own data centers.
Panmnesia found that its next-stage CXL controller and PBR** (Port-Based Routing) switch—both design-optimized and built in real silicon—keep memory-access latency low while significantly extending memory expansion to span dozens of servers or more.
Meanwhile, Meta reported that using CXL to expand memory in production services cut the number of servers needed for distributed AI inference by up to 25% and shortened the average response time of its distributed caches by about 29%, delivering gains in both cost and performance.
The results of both demonstrations were vetted over roughly six months by a panel of industry and academic experts (a peer review), which affirmed their validity, and were presented back-to-back in the Industry Track of ISCA 2026*** in Raleigh, USA, on June 29 (local time).
“Bringing the two demonstrations presented at this year's ISCA together, we can conclude that—across the entire path, from controller and IP (intellectual property) design to silicon implementation, routing, operating-system support, and large-scale deployment—CXL is ready for practical use in the data center,” said Myoungsoo Jung, CEO of Panmnesia. “That these validations have now won formal recognition from the expert community, we believe, signals that CXL could see wide adoption in the near future, as demand for memory keeps rising.”
*CXL (Compute Express Link): an interconnect technology that links a range of system devices such as memory, CPUs, and accelerators. It is particularly well suited to lowering the cost of expanding memory capacity.
**PBR (Port-Based Routing): a method of routing data based on the identifier (port ID) assigned to each device. Unlike Hierarchy-Based Routing (HBR)—used in PCIe and early-stage CXL, which could only connect devices in a tree-like hierarchical structure—Port-Based Routing lets devices be connected in flexible topologies. Such an interwoven structure of devices is called a ‘fabric,’ by analogy to woven cloth.
***ISCA (International Symposium on Computer Architecture): the most prestigious global conference in the field of computer architecture.
